ip2soc.com
Engage and we Empower you to Excel!
Our service offering:​​
-
Data driven personalized medical devices.
-
Support IP developers in design simulations.
-
Specialized training in IC design methodology.
-
Support the customer in the SoC design flow.
-
Engagement with foundry partners for test-chip development.
-
Standard cell, IO and memory characterization.
News!​​
-
We have signed an agreement with TowerJazz foundry for designing test-chips using their IP!
-
Technologies enabled : 130nm, 180nm and 300nm RFCMOS processes.
​
​
ASIC design training
Our state of the art training sessions have been created with one goal in mind; providing people with an affordable, user-friendly learning platform. On-site projects and tutorials are intended to provide the users with a flavor of the work involved in the semiconductor design industry and an opportunity to learn new skills.
​
This session will include some examples of logic synthesis, standard cell library offering, library views used by CAD tools: layout, LEF, library characterization following by verification.
​
Static Random Access Memory : SRAM
This session will cover memory classification, SRAM bitcell, stability, read/write in SRAM, timing in SRAM, memory compiler, layout etc...
​
Dynamic Random Access Memory : DDR memories (under development)
This session will cover memory classification, DRAM bitcell, read/write operation in DRAM, read/write timing in asynchronous DRAM, JEDEC standard for refresh, DRAM subsystem organization, SDRAM, DDR memory interface, synchronization, custom layout, training modes etc...
​
This session will cover the essentials of Static timing analysis, False paths, Multi-cycle paths, Half-cycle path, lock-up latches, run complexities in STA : CDC, OCV, SI, MMMC etc...
This session will cover the basics of SoC design flow : Design import, MMMC, Extraction, Floorplan, Placement, Clock tree synthesis (CTS), routing, sign-off to finished design.
​
This session will cover the basics of IC layout essentials. : Placement of well and substrate taps, shielding of critical nets, antenna fixes, DFM, ERC compliance, power grid and de-coupling capacitors, diodes attached to input pins, double patterning, common centroid layout etc...
​
Projects :
1. Design, implementation and analysis of linear feedback shift register circuits.
2. 8-bit signed binary multiplier : design and analysis (booth multiplier included).
3. Design and implementation of a 8-bit floating point adder.
4. Design and implementation of a multicycle MIPS processor.
5. Implementation of 7-tap linear phase FIR (Finite impulse response) digital filters. (under development)
​
ip2soc.com
STDCELL CONTENTS
Logic synthesis: Synthesizing a design using standard cell foundation IP.
Synthesized gate level logic : FSM -> RTL -> Netlist
Standard cells like LEGO blocks.
Typical standard cell offering.
Voltage domain crossing : Level shifter cells.
Power gating cells for collapsible domains.
Clock gating cells : Dynamic power mitigation.
Clock domain crossing (CDC) cells.
Files in a library (.v, .lef, .gds2, .sp, .lib, .cdev, .spcurrent).
CMOS Inverter layout.
Layout versus abstract view.
Behavioral Verilog models.
Physical views : gds2 and lef.
Spice netlist.
Liberty models.
Redhawk models.
Standard cell Characterization : NLDM versus CCS.
Standard cell verification : Spice versus verilog versus .lib.
Thank you!
SRAM memories
Memory classification : Non-volatile (ROM) and volatile (SRAM, DRAM) memories.
Memory organization.
6T SRAM versus 1T-1C DRAM bitcell.
Write operation in a 6T SRAM bit-cell array.
Sense-amplifier in SRAM.
Read operation in a 6T SRAM bit-cell array.
Stability of 6T SRAM bit-cell : Static noise margin.
Access time components in an SRAM.
Reducing access time. C∆V/I (architecting the memory)
Cycle time : Read after a write.
Replica based self-timing.
Memory leakage mitigation (80 nW/bit?) : Standby, retention and sleep modes.
Half selected bit-cell.
Read/write assist techniques.
Redundancy and error correction.
Memory compiler and layout.
π3 modeling
Memory Characterization.
Memory testing : Embedded BIST
Thank you!
STA CONTENTS
Motivation for static timing analysis.
Inputs/Outputs : STA tool.
Different timing paths in STA.
Register to register path : PT commands/reports.
Input IO to register path : PT commands/timing report.
Register to output IO path : PT commands/timing report.
Input IO to output IO path : command/timing report.
False path/Multi-cycle path/Half cycle path.
Lock-up latches : scan chains.
Run complexity of STA.
MMMC : Multi-mode multi-corner analysis.
MMMC Primetime commands.
Extraction corners : Cmin, Cmax, Ctyp, RCmin, Rcworst.
OCV : Max analysis.
OCV : Min analysis.
SI : Timing windows.
OCV + SI : Effect of Xtalk - Max. analysis.
OCV + SI : Effect of Xtalk - Min. analysis.
Example (rtl2gds) : Sequence detector.
Thank you!
SOC CONTENTS
Physical design flow.
CAD tools.
MMMC: Multi-mode multi-corner analysis.
MMMC tcl commands.
Extraction corners : Cmin, Cmax, Ctyp, RCmin, Rcworst.
Floorplan.
Placement goals.
Simplistic placement : Minimize ‘virtual net length’ - HPWL.
CTS objectives.
Clock tree routing.
Routing.
Maze algorithm.
Sign-off : DRC, LVS, ERC, Density, Antenna, EM-IR, DFM, STA, ATPG, Equivalency.
Antenna violation.
Antenna fix.
DFM violations : Yield enhancement fixes.
Thank you!
​
IC LAYOUT
​
FinFet versus CMOS.
Layout of a differential amplifier : Common centroid layout.
Standard cell layout.
Double patterning and variability.
Antenna fixes.
DFM : Yield enhancement techniques.
Shielding of critical nets.
Placement of well and substrate taps : Latch-up concerns.
Input clamping : Reverse biased diodes attached to input pins.
Power grid planning (de-coupling capacitors attached to grid).
ERC compliance : Level shifter example.
OPC : Optical proximity correction.
WPE : Well proximity effect.
Thank you!
...
​